1. Field of the Invention
The present invention relates to a multi-layer plastic package within which a semiconductor chip is accommodated, and in particular to an innovative structure for a multi-layer plastic package within which a power source bonding pad and a power source plane layer are directly connected through the side wall of an opening in order to reduce the inductance of a power source.
2. Related Arts
A plastic pin grid array package (PPGA), or a plastic ball grid array package (PBGA) has become popular as a package for accommodating an LSI chip for which large number of input/output terminals are required. For example, a large LSI chip which requires the large number of input/output terminals, such as ASICs, can be accommodated within a package in which external terminals are arranged in the form of a grid. A multi-layer structure is employed for such a package because in addition to a signal wiring layer for the connection of signal input/output terminals, power source plane layers are provided for a supply of power and for a ground.
Instead of a conventional package, wherein are laminated a plurality of ceramic substrates, a plastic package has been proposed for use as a multi-layer LSI package. In the design of the plastic package, similar to a printed circuit board, core layers made of resin and formed conductive layers, and pre-impregnated layers, which are also made of resin, for bonding with the core layers are laminated.
With recently available devices, frequency and power consumption tend to be increased, and an appropriate structure for these factors is required for a package in which a chip can be accommodated. For example, first, a package is multi-layered, with a power source plane layer and a ground plane layer being provided in order to ensure the supply of a constant, large current. Second, the inductances in the power source plane layer and the ground wiring are reduced to the extent possible. Third, a power source and a ground plane layer are sandwiched between signal wiring layers to match the impedances of the signal lines. Fourth, crosstalk occurring between the signal lines is reduced. And finally, the change of the potentials in the power source and the ground are reduced to the extent possible.
In line with the above, a package has been proposed wherein a grounding bonding pad and a grounding plane layer are directly connected using a side wall conductance layer, which is formed on the side wall of an insulating layer.
However, with the conventionally proposed package structure, inductance can not be reduced for both a power supply source and a ground power source (in this specification, the power supply source and the ground power source are called power sources. Therefore, the power supply source is referred to as a first power source, and the ground power source is referred to as a second power source).
Furthermore, recent LSI devices have a plurality of types of power supply sources and a plurality of types of ground power sources. For such a device, the power supply source and the ground power source must be separately provided for a package prepared for the accommodation of an LSI chip. And it is difficult to reduce the inductance of all of the power sources.
In addition, since a side wall conductive layer is provided, a short circuit may occur with a bonding wire that is connected to a signal bonding pad. Further, a die attachment material on a die stage may short-circuit with a side wall conductive layer by forming a side wall conductive layer.
A package structure which can satisfactorily cope with the many conditions enumerated above has not yet been proposed.